Currently, an increasing amount of intellectual property (IP) circuits are being integrated into individual chips. The IP circuits may be designed by different IP vendors. When the chip is fabricated by a fabricator, the fabricated chip may undergo a failure analyzing process to determine if failure occurs in the fabricated chip. If failure occurs in one IP circuit, the whole chip may be sent back to the corresponding IP vender to diagnose the failed IP circuit because the fabricator may not have enough information to diagnose the failed IP circuit. The original IP vender may require an extended time to determine the cause of the failure. As a result, the throughput of the fabricator may be severely affected by the efficiency of the IP vendor. Moreover, when the whole chip is sent to an IP vender, the other IP circuits are also exposed to the IP vender, which may result in confidentiality issue.